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Radio - Servo - Gyro - Gov - Batt > Homebrew PCM Receiver: QPSK/RF Design
 
 
Phil Cole
Veteran
Location: Redwood City CA

My Posts This: Topic  Forum

Mark,

That paper explains things better than I could have.

Part of the problem of using digital parts for analog purposes is that they are not characterised in the way that they are used for these application.

So, it's lucky that the video switches actually do the job. There could have been differential delays in the the paths to the switch elements from the decoder. This would not have affected the way it performs it's intended function.

The reason I leapt to the ECL bandwagon is that it does not saturate the transistors. This means you don't get assymetrical behaviour due to different delays for transistors going in and coming out of saturation. Of course FETs don't saturate like bipolar transistors, so there is more of a change that CMOS logic will work better than the bipolar saturated logic families.

My first job after graduation was with a marine radio company. They used the phasing method with direction conversion for SSB generation and reception. The quadrature LOs were generated by two ECL flip flops similar to the way the Tayloe detector works. It was necessary to use ECL to get the required sideband suppression (something around 50 dB) even though the highest signal frequency involved was only about 8 MHz. CMOS, TTL , etc. just didn't get the job done. This was in the early 80s, and the saturated logic families have improved a lot.

Still, the SDR is quite an achievement. I suspect there was a lot of subtle optimisation involved in getting it to work as well as it does, despite its simple appearance.
09-19-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, Phil!

Please don't misunderstand my reaction - I absolutely agree with you that ECL is the best conclusion so far. It's just that ECL is so...

Back when I worked at Zenith Data Systems in the mid-late 80s/early 90s, the engineering team there was the industry leader in portable PC power management. It's in my blood, and I've been a power (consumption) fiend ever since! On top of that, it's astonishing to realize that we'll have to pay as much for two flip-flops as we will for the entire DSP/CPU (sad, but true)! I guess that there's something to be said for comfy niche markets, eh?

So far, I can only find one way to avoid most of the ECL logic - not counting an FPGA or a custom chip - and that's the Lattice ispGAL 22V10AV-23, a 2.3 nS PLD. Its maximum clock speed with feedback is exactly 312 MHz, which matches the maximum design frequency of the PLL that I'd shown earlier (the max actually required for operation in the 75-76 MHz band is just below 304 MHz). Unfortunately, the ispGAL's power consumption would very likely exceed that of the ECL components at these clock rates, and we'd still need a bit of magic to feed it the input clock. The one thing that's tempting about this approach is that we'd have more flexibility, like the ability to easily change between the mux approach and individual QuickSwitches if performance demands.

Your point regarding "deceptive simplicity" couldn't be more accurate. Attempting to replace Gerald's elegant, but power-hungry, quadrature clocking scheme has been quite a challenge. In addition, after reading through his QEX articles, it appears to me that the current SDR-1000 w/RFE is at least his fourth major revision of this concept! Your point is a good reminder: some degree of experimentation will probably be required to implement the QSD approach at these frequencies with standard logic.

It's very cool hearing about your phasing radio experiences - thanks for passing them along! Those must have been a ball! After we'd discussed the "phasing receiver" earlier in this thread, it's certainly amazing to see how it has been completely transformed in the form of the QSD/QSE. Indeed, kudos to Gerald for pulling it off! Hopefully, we'll be able to come up with a way to leverage that great work here!

Have Fun!
MarkF
09-19-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, Gang!

I've made a couple of improvements to the PLL that are encouraging. First, by changing to a slightly different VCO from Premier (the V0305-05), we can get a guaranteed output level of +7 dBm, which is more than 500 mV. This is interesting, for it should make the output voltage swing great enough to directly trigger the inputs to the ispGAL PLD, if they're configured for the "3.3V PCI" interface mode. If we decide to go that route, note that phase noise in a comparator-less direct-drive scheme like this will be higher than with the nice sharp Analog Devices ECL comparator, though I have no idea how much higher it'll be. Still, at least it's nice to have an alternative!

At the same time I was playing around with that, I also decided to experiment with the PLL step size. With the same PLL chip and VCO, it's possible to move to a 1 KHz resolution in the synthesizer. This is another nice alternative, for it provides the option to implement a combination hardware+software automatic frequency control! With the 10 KHz resolution of the initial synthesizer, it would have been necessary to come up with an algorithm for tracking carrier frequency errors entirely in software. Using the 1 KHz synthesizer spacing lets the software drive the hardware to lock the synthesizer to the actual received signal. Once we're within +/-1 KHz, standard baseband carrier frequency/phase recovery code can finish the job of locking on to the actual carrier phase. There is a slight phase noise price to pay for the 1 KHz step size, but it's still helpful to know that either approach is feasible. As time progresses, we can decide which scheme will work out best.

Cheers!
MarkF
09-19-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, Phil!

While I'm sure that driving the ispGAL with the VCO won't match the phase noise performance of the ECL comparator, I'm wondering whether or not it might be worth giving it a try? The thought here is that this PLD is so fast that the input switching aperture range might just be small enough to make this worth considering. The interesting part is that it would only be necessary to breadboard two components onto a good ground plane - the VCO and the PLD - and it should then be possible to measure the actual phase noise (oh yeah, we'd need bypass caps and terminator resistors, too!).

Does this sound like a waste of time, or do you think it might be worth pursuing? In order to measure phase noise, do you just look at a spectrum analyzer, or is a more involved process necessary?

Thanks again!
MarkF

P.S. On second thought, it may also be necessary to include a low pass filter after the VCO, since it only offers 10 dB attenuation of the carrier harmonics in stand-alone form. What do you think: does it make any sense to try this without the low-pass filter, or do you need the whole solution to estimate the actual phase noise?
09-19-2004 Over year old.
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Bezjak
Heliman
Location: Boca Raton, FL

My Posts This: Topic  Forum		Hello Mark and company,

I have been following your thread with quite a bit of interest. Until seeing your pointers on RunRyder, I did not even know that the mixing approach used by the SDR-1000 existed. That's what I get for letting my subscriptions to QST and QEX expire years ago.

I work for Sunair Electronics (www.sunairhf.com ) and I have had the opportunity to design synthesizers for two of our radios. One of the toughest problems I faced was reducing the influence of vibration on the synthesizer outputs. When you shake a VCO, you get sidebands at the vibration frequency and often its harmonics.

This is because the vibration causes mechanical stress which changes the values of the frequency determining components. This is most prevalent in the inductors, but it also affects the capacitors.

For RC receivers, vibration performance is pretty critical since the receiver is subjected to it whenever the engine is running. On the positive side, you get to use foam to isolate the receiver from the airframe, so this all may be a non-issue. All of the synthesizer testing that I have done had the equipment rigidly mounted to a vibration table, so I can't say how much of a benefit the foam will give you.

The upshot of all of this is that I think it is an excellent idea to get a VCO up and running in the early design stage to look at the phase noise. Then strap it to your helicopter and take another look.

We use a spectrum analyzer to measure phase noise.

Greg
09-20-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, Greg!

The Quadrature Sampling Detector approach really is fantastic! It is amazing that after 110 years of RF, along comes a truly new architecture! I'm extremely fortunate to have stumbled across Gerald's site, and his very well-written articles in QEX.

Welcome to the thread! It was fun checking out Sunair - it looks like you guys design some neat gear! Perhaps there'll even be a QSD-based rig in your future?

Thank you very much for the excellent advice on vibration! That's perhaps the one significant benefit of having to run the PLL at such high frequencies: inductors and capacitors start to get so tiny that their mechanical resonance points will probably be pretty high, too! The crystal will obviously be a concern, but just about everything else will be SMT in the LO chain. Once we get past the LO, probably the biggest concerns will be the 1:4 transformer that precedes the QuickSwitches, and the front-end L-C bandpass filter.

After reading your advice, I read a writeup in the HF Radio Systems & Circuits book on vibration sensitivity in direct-conversion receivers. It points out that RF amps are virtually a necessity with direct conversion (though not commonly used in superhet receivers), since antenna vibration can otherwise induce all sorts of interesting problems. Given that our antennas are just about as bad as you can get in this sense, it will definitely be worth paying very close attention to!

By the way, after playing around more with the PLL design program, it turns out that the cost of a smaller VCO step size is worse than I'd originally thought. With a 40 KHz loop step size, (for a 10 KHz LO increment), the RMS phase error is three times higher than a 4 KHz loop step (1 KHz LO increment)! Since we're using QPSK, RMS phase error is the primary figure of merit for synthesizer quality - this error directly perturbs the received data points away from the ideal QPSK signal constellation points. I guess that we'll have to work a little harder to figure out how to perform carrier frequency recovery solely in software!

Well, I just can't resist giving this direct-drive scheme a shot with the Lattice PLD, so I've sent off quote requests for the PLD and the VCO. It's probably going to take a while before we can do any real breadboarding; Premier is based in Shanghai, and they apparently don't even have a local rep! Meanwhile, as a backup plan, I'll also be looking at an ECL-based solution, just in case the direct-drive scheme doesn't perform well.

Thanks again, folks, for all the terrific help!

Good Luck!
MarkF
09-20-2004 Over year old.
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Bezjak
Heliman
Location: Boca Raton, FL

My Posts This: Topic  Forum		Mark,

Actually, my boss wants to evaluate the SDR-1000. I wrote a purchase order out for one, and I am waiting to see if it is approved by management. I don't think that the image rejection is sufficient for our applications, but it will be fun to take a few days to make measurements of a new architecture.

I hope you don't have too much trouble getting a hold of a VCO. I am interested to see how they perform in this application.

Good luck,
Greg
09-21-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, Greg!

Getting paid to play with ham radio... nice! I hope that the purchase order is approved - I'd love to hear of any quantitative tests that your company might let you share with us!

I'll let you know how the acquisition process goes, as well as the results of any breadboard tests. If the Premier folks take too long, there's another alternative source for VCOs that looks to have better support, as well as a much broader range of VCOs: check out Z-Comm's VCO Products. I'm sticking with the Premier part for now since the National PLL calculator had it in its database, but Z-Comm looks like they could be a good outfit. In particular, they also have some much smaller VCO packages available.

Oh, I did get a quote on the Lattice part: it's about $4.40 in hundreds quantity - not bad at all. I've also discovered that you can program this little beast in-circuit with a ~$60 cable and with ~free software, instead of needing to buy a device programmer. Very nice!

I'm just keeping my fingers crossed that the "direct-drive" combination is going to work out OK - time will tell!

Cheers!
MarkF
09-21-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, Folks!

One thing that happens when you begin playing with software radio is that the initial view is one of tremendous complexity, but as you learn more, the veil slowly begins to lift, and things begin to seem a bit easier. One of the most interesting such experiences occurred when I discovered how incredibly easy it was to move from baseband modulation to carrier-based modulation earlier. After all the modulation theory, the filtering that would seem to be inevitable, etc, it turned out (as I'd posted earlier) that the solution was just to output: I, Q, -I, -Q... Amazing!

I had another one of those experiences today. If you go scouting on the web for a method to generate quadrature clocks, you'll spend a lot of time staring at phase-shift networks and all pass filters - complex stuff! Then, in the digital realm, it's Hilbert transforms and the like. Eventually, you'll come across the Johnson counter. As I sat down to figure out what logic would be necessary in the Lattice chip to generate the quadrature clocks on two registered output pins, it turned out to be:

Out_1 = ! Out_2;
Out_2 = Out_1;

There are moments when you can really begin to appreciate digital/software radio!

Have Fun!
MarkF
09-21-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Good Morning, Gang!

A few more thoughts on the Lattice PLD approach. PLDs are often fairly poor candidates for high phase precision, thanks to the fact that all the random logic in the devices can wreak havoc with the on-chip power planes (that's one reason why many fast PLDs have different specs for the time for a single output to transition, and for all outputs to transition). However, the way that we're using this part ought to make it a much better candidate for higher precision.

The logic shown above translates into a single logic term for each output. Each 304 MHz output clock, only one output will always be transitioning from low to high or high to low. This should result in clean power planes, meaning higher accuracy detection of the input level switching points. In addition, the very tiny 'QFN' chip scale package that the chip is packaged in delivers low impedance pin connections, further giving it a stability boost.

Now for the bad news. Unfortunately, this tiny package will be a bear to prototype with! Unlike my initial thought of slapping a few parts onto dremeled-out unetched board stock, it may well be necessary to fabricate an L.O. test PCB to properly measure the phase noise. If we do go that route, I'll probably include the synthesizer chip, too - we might as well measure the total performance of the L.O. chain. While this is starting to become a pretty significant time investment in an obviously speculative approach, it's probably worth doing right. I'll continue to think this over, but it's sounding as though it may be time to pull out the Eagle PCB design program!

Best Regards!
MarkF
09-21-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, Gang!

The quote came back from Premier. I'm sure that it could be bettered with a bit of negotiation, but the standard 1K price they responded with is about $7.80 - not too bad. I guess that I'll proceed with a sample order, which will apparently take about two weeks. It looks like I really am going to have to start creating a PCB!

Cheers!
MarkF
09-22-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, Gang!

Yahoo! I've been doing a bit of communicating in the background, and have received some great news! First, kudos are in order. About two weeks after I received the Blackfin evaluation board from Digi-Key, I received a couple of interesting emails from Digi-Key offering special assistance to purchasers of the Blackfin evaluation board. The second one came directly from one of their applications engineers offering to help out personally - quite an unusual level of support! I decided to take them up on it and asked a very important question that wasn't documented anywhere else: "What is the actual analog input bandwidth on the BF-533 EZ-Kit evaluation board"? Fully expecting that the answer would be 20 KHz, I was delighted to learn that the analog front-end bandwidth is in fact 230 KHz!!! In other words, only the 96 KHz cutoff of the A/D's on-chip digital antialiasing filter will restrict the input bandwidth.

This is terrific news, for it means that we can run at full speed, with the actual 24 KHz carrier, right on the evaluation board! That means that we'll be able to prototype perhaps 85%+ of the code before the custom hardware will be necessary! Sure, some changes will be required for the "real" hardware, but they'll primarily be related to initialization, synthesizer control, AGC functionality, and the final servo driving interface (even here, I'll probably be able to wire up the L.O. test board to connect to the evaluation board to test synthesizer control).

So kudos, indeed! To Digi-Key, for a very impressive level of support, to Paul Fuchs, the Digi-Key application engineer whose friendly, persistent, and knowledgeable assistance drove the answer directly from ADI (despite the fact that I'd explained to Paul that this was just a hobby project!), and to the unknown engineer at Analog Devices, for doing the Right Thing when s/he designed this evaluation board. Thank you very much, folks!

I'm amazed, but this little puppy's actually starting to come together! Yahoo!

Best Wishes!
MarkF
09-23-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, Folks!

One quick personal note. If you've been following this, you've no doubt noticed by now that I'm more than a bit dyslexic. As a consequence, I keep posting stuff like the "QDS - Quadrature Data Sampling" architecture versus the (correct) "QSD - Quadrature Sampling Detector" architecture, along with similar errors. Please accept my apologies, but it seems that I can't write to save my soul - I can only edit my way to anything that's even remotely readable. Perhaps your best bet is to stay a few days behind anything that I post...

Anyway, to those of you who've hung in there despite my frequent mistakes, thank you very much! My commitment to you is to work hard to come up with an end result that's genuinely useful, whatever detours we may take along the way. Thanks again.

Cheers!
MarkF
09-23-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, Gang!

In preparation for testing the L.O. strip (no, I haven't started designing it yet, but I'm trying to look ahead), I've spent the last few days hunting around for a low-priced Scalar Network Analyzer. Gulp! For those who aren't familiar with this type of equipment, it doesn't sniff Ethernet, but instead is used to measure the ~impedance, frequency response, and S-Parameters at individual nodes on an R.F. design. Since it's difficult to know the precise capacitance and inductance of every trace and component after assembly, the network analyzer lets you peek in to the design in detail, and you can then tweak the component values to achieve the performance that you're looking for. As one example of how they're used, when we first brought up a new QAM-256 modulator design at work, the lead engineer spent a few weeks poking at every node on the board with the network analyzer, and by the end had managed to reach the desired spur and phase noise performance. Very handy, indeed!

Unfortunately, they're extremely expensive. While you can rent them, the rental fees are upwards of $1,000/month! I thought I was getting close to winning with a bid on an eBay auction (for a used Wavetek/Giga-tronics 8003 plus an HP sweep generator and power module), but in the last hours the price nearly doubled from the highest amount I was willing to pay. This is indeed a challenge.

I did discover another alternative, and I'm interested in your thoughts. N2PK has developed a very cool little PC-Based Vector Network Analyzer that looks as though it would do the job well (as long as it were outfitted with the narrowband extension options). However, this looks like it could easily take a couple of months to build itself - some of the components are apparently quite difficult to source. Still, it would be considerably less expensive, and quite probably would teach me a lot more about RF.

So, for those of you who are familiar with network analyzers and their utility, I'd love to hear what you think. Are they indeed as useful/essential as I've come to think they are? I'm a bit hesitant to go through the effort of building up the N2PK VNA system for the further delay it'll induce in this project, but money is an issue. Rental isn't much of an option, since realistically this project is going to take a long time, with the L.O. strip test PCB first, eventually a couple of passes on the receiver PCB(s), then ultimately the transmitter, etc.

I'd greatly appreciate any suggestions or recommendations you may have! Thank you very much!

Have Fun!
MarkF
09-25-2004 Over year old.
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RC-CAM
Senior Heliman
Location: USA

My Posts This: Topic  Forum		I've trolled eBay for the last two years trying to get an affordable deal on a good network analyzer. There have been some great deals ($40K box selling for $8K), but still way beyond my budget. So, I'm still looking.

My advice is to get chummy with someone at work that has the equipment. Your project will be much better off if you have access to this test equipment.

RC-CAM
09-25-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, RC-CAM!

That's definitely a great idea, but I forgot to mention that the network analyzer we were using at work was only borrowed at the time, and is no longer accessible to us. Rats! Hmmm... it's probably overkill to change jobs... (just kidding). Maybe it's time to refinance my house? Muhaha...

I'll see what I can come up with. Thank you very much for confirming that this is indeed a worthwhile pursuit!

Cheers!
MarkF
09-25-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, RC-CAM!

Well, after losing out on yet another network analyzer bid (when somebody slammed the bid up by more than $400 in the last 25 seconds), I finally broke down and splurged on a very nice setup. I've purchased an Advantest R3762AH with R3961T S-Parameter Tester through eBay. Gulp! It's a scary purchase, but the seller is very reputable. What makes the investment a bit less frightening is that my employer may well be interested in buying it from me once I'm finished with it. Either way, it's pretty clear that network analyzers hold their value quite well.

I've obviously got a great deal to learn to be able to exploit this instrument properly, but it should certainly do the job, with coverage from 300 KHz-3.6 GHz and up to 100 dB of dynamic range, along with measuring so much stuff that I haven't even heard of some of the parameters!

Now we're really committed! If I don't take advantage of this puppy and get some results, I suspect that my girlfriend would kill me. I do have to say, though, what an amazing girlfriend I have. I obviously didn't take her up on it, but can you believe that she actually wanted to help me pay for this? WoW, I'm lucky!

Now it's time to get my butt in gear and get back to designing!

Have Fun!
MarkF
09-26-2004 Over year old.
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RC-CAM
Senior Heliman
Location: USA

My Posts This: Topic  Forum		Looks like you are set with test gear. I'll bet the credit card is still smok'n!

RC-CAM
09-26-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Hi, RC-CAM!

You aren't kidding - in fact, it took some rather creative account transfers just to make room for it. I'd seen the Advantest all along, but had summarily rejected it, thinking it was too expensive. However, after going through two rounds of auctions (each of which tied me up for a couple of days doing research, background checks, etc.), both of the auctions closed between $4,500 and $5,000. When you first scan eBay, it seems like the going rate for network analyzers is more like $2,500-3,000, but as I found, the pricing skyrockets in the last hour. With prices for inferior gear that high, the $6,000 "Buy it Now" price for the Advantest became more acceptable. Err... well, at least worth striving for! Seriously, the specs on the Advantest really are better than the other gear I'd considered, so it's not like I had to "settle".

There'll be more to dig up or make, I'm sure, like probes for in-circuit testing, directional bridges, etc., but at least the big ticket item is definitely taken care of.

I think I'll be eating a lot of Kraft Macaroni & Cheese for the next few weeks!

Have Fun!
MarkF
09-26-2004 Over year old.
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MarkF
Senior Heliman
Location: Palo Alto, CA

My Posts This: Topic  Forum		Howdy!

I discovered a great introductory course called Network Analyzer Basics from Agilent that's a very good read. It's long (110 slides), but it covers everything from the basic theory of transmission lines, Smith Charts and S-Parameters up through error sources, calibration, and measurement setups and techniques. A particularly important "ah-hah!" for me was realizing how network analyzers make it possible to close the loop between design and real world performance, since the S-parameters measured by a network analyzer can feed back directly into simulation models - very nice!

Now, one point that wasn't covered, but I suspect will be possible, was how to use a network analyzer as a spectrum analyzer (naturally, Agilent would rather sell you both). After having made this investment, I'm interested in figuring out how to configure the network analyzer to do double-duty. Sure, it won't be exactly the same, since the network analyzer's max 1 KHz IF bandwidth is probably too low for the usual real-time full-band spectral display. Still, I'm hoping that we can come up with a configuration that's useful enough to be able to avoid the need for a conventional spectrum analyzer for most of the needs of this project.

Does anyone have any experience in this vein, or is this just wishful thinking?

Happy Flying!
MarkF
09-27-2004 Over year old.
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