MarkF
Senior Heliman
Location: Palo Alto, CA
My Posts This: Topic Forum | Hi, Gang!
It's been a productive morning. I played around with National's PLL calculator long enough to discover that we'll be able to get there without too much difficulty. One reason for the confidence is that their interactive design program recommends specific integrated VCO (voltage controlled oscillator) modules, instead of performing this discretely with a varactor diode. This is actually an excellent idea for someone who is as new to RF hardware design as I am. With all PLLs (hardware or software), debugging can be a bit tricky. By using an off-the-shelf VCO, we'll know that the oscillator is fine, and all that will be necessary will be to tweak the phase detector and gain controls. Please accept my apologies, Phil, I hope that I'm not wimping out too much on you! 
Actually, given the degree of sophistication of National's analysis program, assuming that we're reasonably careful during PCB layout, there's a very good chance that the synthesizer might just work! Power isn't an issue either, with <10 mA needed in a variety of different synthesizer chips. It looks like we'll have a solution with this approach. One significant caveat: I haven't been able to get pricing yet on the recommended VCO modules (fortunately, it does appear that some of them target high-volume, low-cost applications).
I've also been continuing to analyze the front-end, trying to understand how to apply the QSD for this application, and have run into an interesting challenge. After staring at quite a few datasheets, I'm a bit concerned about switching time. As we've already discussed, the time required for the QuickSwitch to transition from one input to the next is very important. Let's assume a worst case of 76 MHz. At this frequency, the carrier cycle time is just 13.16nS. Since the individual phase capacitors are connected for 1/4th of the cycle (i.e. 90 degrees), that means that each cap should be connected to the RF input for just 3.29ns. Here's the issue: the specification for the worst-case switching time on the QuickSwitch in the SDR-1000 is 9 ns! That certainly seems to be a problem.
Strangely, though, the SDR-1000 works at 6M, and from the posts on the Flex-Radio forum, it seems to work well there. At 54 MHz, each phase lasts only 4.63 nS, so it shouldn't be working at all - at least not in the traditional worst-case design sense. Let's assume that the caps needed to be connected for 3nS for reasonable performance. Following worst-case design principles, that would mean a maximum carrier frequency of 1 / ((9ns + 3ns)*4), or just 20.8 MHz, yet the spec is 65 MHz. In other words, without implying any criticism at all, Gerald's design relies on an undocumented assumption of how the switch operates internally.
Now, some folks would automatically declare this to be a bad design. In this case, though, I disagree. To state the unstated, the underlying assumption is simply that the switch will have roughly similar connect and disconnect delays. Under that assumption, the 9 nS time interval isn't spent being disconnected, it's spent being connected most of that 9 nS. Conceptually, this relies on the switched outputs having a ~25% duty cycle (or something close to it), with there simply being a 9 nS latency between the input selection pins and the capacitors. This is the sort of assumption that isn't unreasonable, especially once tested, since it is very unlikely that the manufacturer will change the fundamental device architecture. Anyway, it obviously works!
Nonetheless, pushing this design out to 76 MHz will certainly land us in the research category. I'm OK with that, but prudence would suggest that we use the fastest, lowest resistance QuickSwitches that we can find. With at best 3.3nS per cycle to help charge each cap, the R-C charge time will be very important!
With this in mind, there's no question that we'll need a +5V power supply - operating the QuickSwitches at lower voltages dramatically slows down the select logic. Now, we'll have to decide later on whether to require a +6V battery (which helps servo speeds anyway), or to incorporate an internal DC/DC for a +5V source. Let's set that aside for now, but we will have to acknowledge the need for +5V.
At least there is one very significant benefit of operating at +5V. Intermodulation distortion products are determined by the linearity of the front end - particularly by the "mixer". In the case of the QSD architecture, that translates into a linear resistance curve for the QuickSwitches. If you'll recall from Part 4 of Gerald's article, Quickswitches tend to have a linear operating region at lower input voltages, then the resistance rises at higher input voltages. Increasing the power supply on the QuickSwitch yields a higher "transition" voltage, which directly results in higher "IP2" and "IP3" (second- and third-order intermodulation distortion figures of merit). As I'm discovering, R/C receivers are more challenged by intermodulation distortion than by sensitivity, so the improvement offered by using 5V is a good thing!
Wow, there's a lot to learn about this little bugger! 
Cheers!
MarkF |
Advice well taken! When I lay it out, I'll try to isolate the L.O. in a corner of the board with its own shield ground, its own power filtering, etc., so that it'll be possible to include an R.F. shield can over the whole thing. As always, that's an excellent point! Thank you very much!
